CMOS ICs are usually powered by an external power supply which provides a VCC voltage suitable for normal chip operation. When the power supply is initially turned on, the VCC voltage rises and ultimately stabilizes at its specified DC operating value. The time interval during which this occurs is sometimes referred to as the "power-on reset interval" or the "cold initialization interval". All on-chip circuits connected to the power supply must be forced into their correctly initialized states during cold initialization. If these circuits are not properly initialized, they could generate false output signals during cold initialization, or even enter the wrong initialized state. Either or both of these possibilities can cause erratic system behavior and, in some cases, can cause system failure.
In a typical application the dc power supply voltage (VCC) is derived from the AC line. In such applications the cold initialization interval cannot be less than 4 ms (1/4 cycle of the 60 HZ AC line). However, depending upon the risetime specifications of the VCC power supply, the cold initialization interval can last much longer.
If the system includes a crystal oscillator, the cold initialization interval must be extended until the crystal warm-up time has elapsed (i.e. the crystal has begun to oscillate at the correct frequency). Since the crystal warm-up time is relatively long (25 ms-250 ms), it is infeasible to utilize an on-chip RC time constant to generate the required crystal warm-up delay. In order to illustrate this point, let us assume a maximum `practical` on-chip capacitor value of 100 pf. (This capacitor value is limited by the chip area consumed by the capacitor; larger capacitors consume additional chip area). In order to generate a 250 ms crystal warm-up delay, a 2500 Megohm resistor would be required. Assuming a `typical` Nwell resistance of 1.5 Kohms/square, this 2500 Megohm resistor would require approximately 1.7 million squares of N-well. These squares would occupy a chip area which is intolerably large. Additionally, the resistor current would not be reliable because it would be extremely small (approximately 1.3 nA at 3.3v). In summary, if the crystal warm-up delay is to be generated on-chip, the on-chip initialization circuit cannot use an RC time constant in order to generate the warm-up delay.
During cold initialization the VCC voltage ramps up from zero volts to its final dc value. Thus, during most of the cold initialization interval, the on-chip initialization circuit must operate in the absence of a fully `valid` VCC voltage. This constraint makes it virtually impossible to employ `standard` analog circuitry such as comparators, Schmitt triggers, etc.
In terms of flexibility, many of the prior art initialization circuits have proven inadequate, due to one or more of the following limitations:
1) They employ an on-chip RC (resistor/capacitor) time constant which provides inadequate crystal warm-up time; PA1 2) They fail to respond to fast power supply risetimes, such as those found in battery powered applications; PA1 3) They do not provide a short test time for the crystal warm-up delay; PA1 4) They are not filly ratiometric to the VCC power supply voltage (i.e. their response depends upon the risetime of VCC, instead of depending only upon the VCC voltage value); PA1 5) They may not operate correctly when the VCC risetime is extremely slow or extremely fast; PA1 6) They provide an initialization signal which is not robust (i.e. the initialization signal is removed when the VCC voltage is fairly low--in the worst case, barely more than the sum of the PMOS threshold and the NMOS threshold); PA1 7) Their VCC trip point varies widely with PT (process/temperature) variations; PA1 8) They employ non-CMOS structures, such as depletion devices, or PA1 9) They are excessively complex.
In view of the foregoing limitations, it should be apparent that an improved on-chip initialization circuit would be highly desirable.